ICs

• CD4027 Dual JK Flip Flop Package IC which operates at medium speed of 16 MHz typically with 10V supply
• Voltage range of 3.0V to 15V
• Static Flip-Flop Operation
• High noise immunity of 0.45 VDD(typ.)
• Set and Reset capability
• TTL compatible
• Low power of 50 nW (typ.)
• Input Rise/Fall time at 5V: 45us
• Maximum and minimum Input Voltage is 2 V and 0.8 V

The Exclusive OR gates are monolithic complementary MOS (CMOS) integrated circuits constructed with N-Channel and P-Channel enhancement mode transistors. All inputs are protected against static discharge with diodes to VDD and VSS.

• Wide supply voltage range: 3V to 15V
• Low power: 100 nW (typ.)
• High noise immunity: 0.45 VDD (typ.)
• Separate SET and RESET inputs for each latch
• NOR and NAND configuration
• 3-STATE output with common output enable

• Inverting IC that can convert High logic level to Low level
• High source and Sink Current as it has the capability of driving 2 TTL Loads at 5V over full temperature range.
• 100% Tested for Quiescent Current at 20 V
• Maximum Input Current of 1A at 18 V Over Full Package Temperature Range; 100 nA at 18 V and 25C
• 5-V, 10-V, and 15-V Parametric Ratings
• It is available in 16 pin packages of PDIP, SOIC, TSSOP, SO.
• Special input protection to protect inputs against static discharges.

• Wide range of digital and analog signal levels: digital 3 – 15V, analog to 15Vp-p
• Low “ON” resistance: 80Ω (typ.) over entire 15Vp-p
  • signal-input range for VDD − VEE = 15V
• High “OFF” resistance:
  • channel leakage of ±10 pA (typ.) at VDD − VEE = 10V
• Logic level conversion for digital addressing signals of
  • 3 – 15V (VDD − VSS = 3 – 15V) to switch analog signals
  • to 15 Vp-p (VDD − VEE = 15V)
• Binary address decoding on chip

The 4077 is a quad 2-input EXCLUSIVE-NOR gate. The outputs are fully buffered for the highest noise immunity and pattern insensitivity to output impedance. The 4077 operates over a recommended VDD power supply range of 3 V to 15 V referenced to VSS (usually ground). Unused inputs must be connected to VDD, VSS, or another input.

The CD4081 quad gate is a monolithic complementary MOS (CMOS) integrated circuit constructed with N- and P-channel enhancement mode transistors. They have equal source and sink current capabilities and conform to standard B series output drive. The devices also have buffered outputs which improve transfer characteristics by providing very high gain. All inputs protected against static discharge with diodes to VDD and VSS.

• Supply voltage ranges from 3v to 18v
• Set-up-time is 150, 70, and 40ns at 5v, 10v, and 15v respectively
• Strobe pulse width is 400, 160, and 100ns at 5v, 10v, and 15v respectively
• Hold time is zero
• 100% tested for quiescent current at 20v
• Having high input current of 1uA (max.) at 18v
• Maximum output current sourcing of 25mA
• Operating temperature ranges from -40 C to 85 C
• Storage temperature ranges from -65 C to 150 C

The DS1307 serial real-time clock (RTC) is a lowpower, full binary-coded decimal (BCD) clock/calendar plus 56 bytes of NV SRAM. Address and data are transferred serially through an I2C, bidirectional bus. The clock/calendar provides seconds, minutes, hours, day, date, month, and year information. The end of the month date is automatically adjusted for months with fewer than 31 days, including corrections for leap year. The clock operates in either the 24-hour or 12-hour format with AM/PM indicator. The DS1307 has a built-in power-sense circuit that detects power failures and automatically switches to the backup supply. Timekeeping operation continues while the part operates from the backup supply.